Fpgatrabajos

VHDL and FPGA lab. USING Xilinx software. See attached file for details.

I want to implement DWT based watermarking alongwith cryptography on fpga. Requirement is it should be area efficient. Then performance is to be compared with DCT based watermarking alongwith cryptography on fpga.

I need someone to seo for my website : A website about FPGA projects and details tutorials, Verilog/ VHDL, MIPS Assembly, Logisim The method should be good and cheapest quote will be selected.

Control the traffic light using fpga

We are seeking an Embedded Systems Engineer to implement our synthesizer RTL. We have 4 synchronized FPGA that need to actuate a large grid of elements and modulate signals in frequency and amplitude.

Hi, i need urgent help with this project. Its due in two days. we use xilinix software. and use fpga board. Specs are posted. I can post the vga interface code if you like. Thanks

Realtime clock using picoblaze microcontroller on Spartan 6 FPGA board. it should show real time and have function to change time using push button.

I need an electronics engineer with about 2 years of experience in programing FPGA's to discuss the project with me. the FPGA chosen is Altera Cyclone IV. The board shall be connected to a USB port and the circuit diagram and all datasheets shall be provided. the FPGA board takes data from the PC on the USB and forwards it to another electronic board and at the same time manages a few motors ( 3 nos) and about 12 sensors. All details shall be provided to the concerned engineer

A system to monitor the coal mine environment using gas sensor , temperature and humidity sensor. If the sensed data is exceeding threshold value then generate a warning using buzzer.

I need help in making a FPGA design project. Which create triangle, sine and square waves. Can change 3 different frequency and 3 different amplitude. More info will be provided.

Description: Offset PPM is a novel coding scheme for use in optical communications (fibre and free-space). This project is concerned with implementing an Offset scheme using discrete logic gates. Timing extraction is not necessary as all timing signals will come from the coder. This is a test of how fast the system can operate and will be compared with the FPGA implementation.

1500 words need to be written for the project planning report. skills: Digital electronics Description: Offset PPM is a novel coding scheme for use in optical communications (fibre and free-space). This project is concerned with implementing an Offset scheme using discrete logic gates. Timing extraction is not necessary as all timing signals will come from the co... skills: Digital electronics Description: Offset PPM is a novel coding scheme for use in optical communications (fibre and free-space). This project is concerned with implementing an Offset scheme using discrete logic gates. Timing extraction is not necessary as all timing signals will come from the coder. This is a test of how fast the system can operate and will be compared with the FPGA implementat...

I need someone who can help me in interfacing of high speed ADS54J20 ADC to FPGA. This ADC uses JESD204B interface at a data rate of 1GSPS with dual channel. So, we have to create this interface using VHDL and capture the data from ADC and store the data using FIFO and make data available on FMC connector which is connected to external ZYNQ board.

hello! I wonder if you can help me with C-programming for a microBlaze processor in a xilinx FPGA. If you don't know microblaze please look it up on google. Let me know if you are interrested. Have a great day!

I am working as a Research Assistant at the University of Applied Sciences Frankfurt, Germany. As a part of a bigger application involving safety assurance systems for banks, I want to implement a Face Recognition System using Local Binary Pattern on Altera-based Cyclone FPGA. I have a working software implementation running on MATLAB but to compare how faster and effective a hardware implementation works, I need a working VHDL Code that employs the Local Binary Pattern operator, where the image captured from a camera is compared with the database stored on a micro-sd card and a corresponding match is found.

Hi ahmedmohamed85, I have a prototype of e...ahmedmohamed85, I have a prototype of energy monitor with 16 channels that works as IoT Hub as well. This prototype was built with Raspberry PI 3 and the code was developed in Python. Do you think we can develop a new version of this hardware using FPGA/SOC to make it cheaper and smaller with advantages than PI ? I saw that there are some FPGAs with SOC and ARM integrated. Do you think we can do better and cheaper ? How long time it takes ? In this case may I use the same hi-level code that I used with PI over BSD and develop new drivers to FPGA interfaces to BSD ? Do you have the minimum estimate of hours to do this job, including Hardware design, PCB routing, and all costs estimate ? Thank you and sorry for a lot of questions in ...

Interfacing Mips datapath with the altera DE1-SOC board.

Looking for expert in FPGA to transform a program and run it into fpga any way that it can be done either Verilog or c or openCL.

I have an algorithm and i need to write vhdl code read any image then apply this algorithm and get me the out put

I am looking for a freelancer to help me with my project. The skills required are Arduino, FPGA, LabVIEW, Microcontroller and Verilog / VHDL. I am happy to pay a fixed priced and my budget is $250 - $750 USD. I have not provided a detailed description and have not uploaded any files.

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Requirements can not be lost. Bus GPMC driver has been implemented and FPGA and Linux direct 2K interrupt driver. After the discovery of the interruption of the data received, with the application layer directly 1-2ms delay, can not meet the real-time needs. Project target: Perfect driving and simple application layer demo, realize the real-time communication of 2K. Can not have the packet loss phenomenon. Requirement： To undertake people need to have GPMC Linux bus development experience and high real-time communication experience. Acceptance criteria: Stability of reading data standards: application layer through a simple demo, read and write FPGA data. Read and write clock signal within 8 hours 2K reliable trigger, not packet loss. If you can develop it in linu...

My project is to transfer data between Hps and Fpga on altera De1 soc board. Fpga side there will be Sdram and from the hps we should be able to read and write the data. The data transfer will be done with through AXI bridges and this hardware part can be designed using Quartus 2 Qsys. Hps can be programmed using C language using altera de-5. Ultimate goal is to transferring data. I am new to this field and don't know exactly what to do. I have created Qsys part( with sdram controller, pll , hps i.e cyclone v , jtag uart) I have successfully created the connections with the master slave AXI Avalon interface. Now don't know how to proceed further.

I want a video in which you have to show that how we connect a FPGA from the Xilinx software . you have to show the complete process for connect the FPGA from the Xilinx software .

Build a filter on FPGA

Need to work on Altera De1-Soc board. Need to make communication between HPS and FPGA. Software used are Quartus 2 Qsys.

lsb based steganography algorithn implenting in fpga with and withou pipelining

I would like to have a PCB layout design for a small circuit with FPGA and Memory. The schematics are available in Altium designer project.

Please see the attached file for an idea of the project.

FPGA

FPGA

We are looking for experienced PCB layout designer to work on a Xilinx Artix 7 FPGA embedded system board. System description: * Xilin Artix 7 FPGA based embedded system. * QSPI Flash, NO DDR * Multiple power modules, including 12V to 45V boost converter * One high speed digital LVDS connected peripherals * other SPI and I2C peripherals, like ADC, temp sensor etc. Job descriptions: * Schematic ready and compiled * Components footprints ready * Mechanical constrains ready * Space critical * board size < 5cm * 5cm * 10 layer or less Requirement: * Previous Xilinx FPGA embedded system PCB layout experience * Experience of BGA fan out * Experience of high speed digital differential signal layout and matching * Experience of high voltage boost c...

I need a Model of OFDM Tx RX designed in System generator FPGA the designer know about system generator software.

I want complete solution for Serial Communication Interface, between PC and my custom FPGA board.

I have an ADC chip 'EV10AQ190' and I want to interface it with Virtex-6 FPGA '6VLX240TFF1156'. The task is to simply acquire the analoge data using FPGA and display it on PC.

Using ailtera DE1 SOC board trying to transfer data from HPS to FPGA through OpenCL software used- Quartus ii The objective is to transfer the data back and forth on DE1 SOC board.

64 chs DAQ, FPGA, 16 bits resolution, 40dB gain (PGA), 20MHz sampling frequency, noise figure 2nV/Sqrt(Hz), ref. voltage Vref=1 volt Vpp, USB connection to PC for data acquisition. Suppose I have 64 sensors which give time dependent data and those data need to acquire simultaneously.

Development of FPGA firmware for data acquisition of high-speed ADC modules and transmitting the data via PCIe The aim of the project is to design and implement a modular FPGA firmware for multi-channel data acquisition, the configured depending on the connected ADC on "Partial Reconfiguration" the FPGA interfaces for data acquisition and transfers the data to the processing via PCIe to an embedded computer. The firmware is used in a new modular measuring system. The modular measurement system has 5 slots, which are provided for the insertion of ADC boards. The slots have a direct connection to the FPGA I / O banks.

The aim of the project is to design and implement a modular FPGA firmware for multi-channel data acquisition, the configured depending on the connected ADC on "Partial Reconfiguration" the FPGA interfaces for data acquisition. skbiswas[at][iith][ac][i] 64 Chs,16 bit system, 60dB gain, noise figure 1nV/sqrt(Hz)

Using ailtera DE1 SOC board trying to transfer data from HPS to FPGA through OpenCL software used- Quartus ii The objective is to transfer the data back and forth on DE1 SOC board.

Donanım Tasarımı; Atmel ve PIC Serisi Mikrodenetleyiciler, SMD Malzeme Operatörlüğü, Analog ve Sayısal Devre Tasarımı Elektronik Kart Çizimi (Şematik-PCB) - Basımı, RF modül kontrollü 8 Röle çıkışlı Donanım Tasarımı ve Yazılımının yapılması. ...Mikrodenetleyiciler, SMD Malzeme Operatörlüğü, Analog ve Sayısal Devre Tasarımı Elektronik Kart Çizimi (Şematik-PCB) - Basımı, RF modül kontrollü 8 Röle çıkışlı Donanım Tasarımı ve Yazılımının yapılması. USB, RS232, Can-bus, DC, step motor uygulamaları, Timer ve İnterrupt uygulamaları. Osilaskop, Sinyal jeneratörü Ve Avometre Kullanıımı. Yazılım Tasarımlarında; MikroC For PIC Arduino c# FPGA Sistem Tasarımı ile ilgili refe...

I have an Altera DE0 board, we need to read analog signal and generate two streams of output: DAC to audio and PWM to motor control. Then the frequencies of the output signals need to be plotted on LCD screen to see visual image of the two data streams. Beginner-intermediate level work, need project at earliest so priority given to those who have necessary equipment to begin work.

A PCB based on the Xilinx FPGA Artix 7 is under development. Remote programming is required and is posible using the Xilinx QuickBoot method for FPGA Design Remote Update. Details on the attached file

Need to implement a 20 in and 20 out switch on an FPGA with slave I2C port. This device will be controlled by a master via 400kHz I2C. In & out Signals will be 3.3V and < 50kHz range. Please recommend a device to put it on.

Job description<br />Job Description: Creates emulation/Field Programmable Gate Array (FPGA) models from a Register Transfer Level (RTL) design using emulation/FPGA synthesis, partitioning and routing tools. Defines and documents RTL changes required for emulation/FPGA. Develops hardware and software collaterals and integrates it with the emulation/FPGA model. Tests and debugs the emulation/FPGA model and collaterals. Defines and develops new capabilities & HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for pre-Silicon and post-Silicon functional validation as well as SW development/validation. Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation pla...

I requiere someone that could read the specs for Xilinx’s FPGA XC7A35T-1FTG256C and recommend where to connect a 500 MHz DAC and a 500 MHz ADC with LVDS interfaces using the IOSERDES modules within the FPGA. Aditional information on the attached specs file

project name : Implementation of OFDM on FPGA with mixed radix 8-2 algorithm using verilog. I want full blocks and input and output waveform also.

This is the project that i done in my final year of Btech. Project is based on the implementation of bpsk modulator and demodulator on spartan 3 fpga board.