To simulate RTL Design of GCD of two numbers in Verilog using Xilinx ISE.

hi, I am a senior digital design engineer, I have a wide knowledge of digital design in ASIC and FPGA using both VHDL and Verilog. I am using Vivado, ISE and Quartise. I will provide you a professional report about your project with citation and scientific formatting. Please contact me to know more about your needs. Regards, moaaz.

Hello, I am an FPGA design engineer having experience of verilog/vhdl based FPGA system design for more than 5 years.

i have 2.5+ year experience in design and verification, i have done 30+ project in verilog/VHDL, i will done your project perfectly and on time, i will provide support after completion of project, thanks and regard kundan vaghela

Being an electrical engineer and having strong verilog experience i am bidding on this project, i can do this project for you in cheepest rates, you may contact me with further details

I am an electronics engineer. I am an expert in verilog and FPGA. I have lots of experience with verilog and fpga. I have used vivado, xilinx ise, vitis, quartus and libero softwares for verilog. I have designed 128 bit multiplier, 32 bit cpu and currently designing risc v based SoC. I have designed factorising numbers in verilog and also implented cpu in FPGA and interfaced FPGA with an Arduino. I will deliver the job perfectly without any hiccups and satisfy your requirements.

I am a graduate from BITS Pilani, where I have worked with FPGA design in-depth. From being the Teaching assistant in Verilog Design lab to having completed a Graduate course on FPGA design to writing the entire image-compression algorithm on Zynq-7000 SoC FPGA board for hyperspectral images in satellites, I can attest I have a good experience of writing clean, synthesizable Verilog code. Especially with Xilinx software. Also, I work full-time in a leading FPGA design company, so that gives me an edge.