Altera DE-1 SoC

Cerrado Publicado hace 7 años Pagado a la entrega
Cerrado Pagado a la entrega

Fixing an existing Data Transfer Project.

Verilog / VHDL

Nº del proyecto: #13233870

Sobre el proyecto

6 propuestas Proyecto remoto Activo hace 7 años

6 freelancers están ofertando un promedio de $207 por este trabajo

ahmedmohamed85

Dear sir I have more than 9 years experience in digital design using FPGA also I already have the Altera DE1 SOC board, please message me so that we can discuss

$222 USD en 3 días
(270 comentarios)
7.5
loi09dt1

A proposal has not yet been provided

$90 USD en 3 días
(83 comentarios)
6.2
ducdctoandh

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I a Más

$250 USD en 3 días
(46 comentarios)
5.4
rohi1710rohi1710

Hi, -FPGA design engineer since last 7 years -Expertise in verilog/VHDL Please find below details of the projects TSMAC Hardware acceleration(3months) The project is to develop hardware acceleration block for TS Más

$250 USD en 3 días
(5 comentarios)
4.6
OlektraGroup

dear Sir i can do this project. I can assure you that if you work with me once, you will always work with me for these kind of projects.

$155 USD en 3 días
(5 comentarios)
2.6