Interfacing DDR3 sdram in zynq using vivado vhdl

Dear sir I have more than 9 years experience in digital design using FPGA, please check my profile, I have done several projects using Zynq and i know how to send data in DDR ram and read it back through either HP port or GP port, and using AXI DMA, please message me so that we can discuss more details waiting your reply Best Regards

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I would like to bid this job because I am really suitable for job description: First: I am an Electronics engineer who is very expertise with VHDL/Verilog. In fact, I have done so many project of VHDL/Verilog(Karatsuba multiplier, Nintendo design, encryption algorithm like Sax Hash, Bernstein Hash, HummingBird...Also, I participated in a Walker Recognition project(data from Camera to Human Detection(image processing-HOG feature and Adaboost) and display in VGA). Besides,,I implemented the image conpression (wavelet transform). Aslo, I have experience in coding Booth multiplier and very familiar with Xilinx tools like ISE. and Vivado. Therefore, I can simulation the projecthe in behavior, post-syntheize... with free hesitation. Especially, in your project, I have a lot of experience in working with vivado vhdl to control DDR3 in Zedboard. Now, I have Zedboard (Zynq) to verify the design for you before sending the code. Also, I am very good in English (IELTS 6.0) and I have several year of researching so I can fully understand your requirement and understand fully about the papers and write the academic report.. Please contact me and let me know if you want any special requirement and do with lower price. Thank you.

I've worked on a project to interface a Virtex-7 chip on a VC709 board and have successfully completed the same. It's part of a bigger project to create a readout card for scientific cameras. The experience can be used for AXI interfacing of a Zynq board. Kindly tell me the requirements, throughput and application.