Imagen de perfil de kulwantsingh16
@kulwantsingh16
Bandera de India Bangalore, India
Miembro desde 17 de diciembre de 2013
1 Recomendaciones

kulwantsingh16

En línea Desconectado
6 yrs of experience in FPGA/Asic design and verification domain verilog/VHDL,system verilog,UVM,OVM,VMM . Working on Spartan 3 and Altera DE1 SOC FPGA boards Worked on tools: Xilinx ise Quartus modelsim questasim VCS Matlab Other skills: C,C++,shell scripting,perl expertise in IP/SOC level design Verification worked on functional verification of various blocks in four ARM based SOC designs worked on Designing SPI,I2C,AHB to APB Bridge,PCS layer 1 gigabyte wokred on AHB,AXI,APB,DDR3, Design verification
$50 USD/hr
15 comentarios
4.2
  • 88%Trabajos finalizados
  • 94%Dentro del Presupuesto
  • 94%A tiempo
  • 29%Tasa de recontratación

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Comentarios recientes

  • imagen de michelhe fpga soft radio $30.00 USD

    “This freelancer tries his best to solve problem, however final result was not delivered. I lost money and time.”

  • imagen de mcpglaydson Project for kulwantsingh16 -- 2 $225.00 USD

    “Excellent developer. I recommend!”

  • imagen de csaikiran86 Interface of ADS54J20 ADC to FPGA using JESD204B interface €100.00 EUR

    “Tallented!! Recommended.”

  • imagen de naserfadhul VHDL & Matlab Codes $100.00 USD

    “Great as always! Thanks for you help!”

  • imagen de TRISHA29 vhdl project €90.00 EUR

    “Thank you very much for your [login to view URL] has e done a very good [login to view URL] is highly Recommended. I Will hire him for more projects in future”

  • imagen de sanasheikh125 HPS and FPGA handshaking and mips data path using altera DE-1 SOC Fpga $250.00 USD

    “This is the second time i hired him for a project, He is just brilliant in his field. Perfect work, completed on time and gave all the explanations. Very Professional and Helpful. Highly Recommended. Will hire him for more projects in future.”

Experiencia

FPGA/ASIC Design & Verification

Jun 2012

FPGA/ASIC Design & Verification using verilog,VHDL,system verilog,OVM and UVM

Educación

B-Tech

2008 - 2012 (4 years)

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