Imagen de perfil de kulwantsingh16
Bandera de India Bangalore, India
Miembro desde 17 de diciembre de 2013
1 Recomendaciones


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6 yrs of experience in FPGA/Asic design and verification domain verilog/VHDL,system verilog,UVM,OVM,VMM . Working on Spartan 3 and Altera DE1 SOC FPGA boards Worked on tools: Xilinx ise Quartus modelsim questasim VCS Matlab Other skills: C,C++,shell scripting,perl expertise in IP/SOC level design Verification worked on functional verification of various blocks in four ARM based SOC designs worked on Designing SPI,I2C,AHB to APB Bridge,PCS layer 1 gigabyte wokred on AHB,AXI,APB,DDR3, Design verification
$50 USD/hr
15 comentarios
  • 88%Trabajos finalizados
  • 94%Dentro del Presupuesto
  • 94%A tiempo
  • 31%Tasa de recontratación


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FPGA/ASIC Design & Verification

Jun 2012

FPGA/ASIC Design & Verification using verilog,VHDL,system verilog,OVM and UVM



2008 - 2012 (4 years)


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