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@kulwantsingh16
Flag of India Bangalore, India
Miembro desde December, 2013
1 Recomendaciones

Verilog/Vhdl/FPGA expert

En línea Desconectado
5 yrs of experience in FPGA/Asic design and verification domain verilog/VHDL, system verilog, UVM,OVM,VMM . C,C++,shell scripting,perl worked onSpartan 3,DE1 SOC board based Digital designs Xilinx ise Quartus 2 modelsim questasim VCS gcc/g++ mingw Linux expertise in IP/SOC level design Verification worked on functional verification of various blocks in four ARM based SOC designs worked on Designing SPI,I2C,AHB to APB Bridge,PCS layer 1 gigabyte wokred on AHB,AXI,APB,DDR3, Design verification
$50 USD/hr
14 comentarios
4.2
  • 93%Trabajos finalizados
  • 94%Dentro del presupuesto
  • 94%A tiempo
  • 36%Tasa de recontratación

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Experiencia

Freelancer Expert

Dec 2013

ASIC/FPGA Design Verification

Design Verification Consultant

Jun 2012

design verification using system verilog OVM/UVM

Educación

B-Tech

2008 - 2012 (4 years)

Certificaciones

Asic Design & Verification Course (2012)

Maven Silicon Softech Pvt Ltd

Asic Design & Verification Digital Design using of IP using system verilog OVM,UVM

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