Experienced Digital IC Design Engineer and RTL Coding Expert,
offering FPGA/ASIC RTL Coding in Verilog, SystemVerilog, and VHDL, with Multilingual Tutoring.
Available Round-the-Clock | Flexible Pricing | Prioritizing Service Excellence
My Experience:
I've worked extensively with FPGAs, utilizing various FPGA boards such as MAX Family, DE-series, Cyclone V, ZYNQ, PYNQ, Basys3, Artix7, and Efinix T120. I'm well-versed in Vivado, Vitis HLS, Quartus, and Efinity for FPGA design.
For ASIC design, I've harnessed the power of Synopsys tools, employing both TCL scripts and GUI. I'm proficient in DesignCompiler, Formality, and DFT.
I am also proficient in documenting designs using three methods: LaTeX, Microsoft Word, and Markdown language.
My portfolio showcases a diverse array of complex designs across fields like image processing, cryptography, communication protocols, and processors, all implemented using HDLs.
Let's collaborate and bring your project to life. Reach out to discuss the details, and I'll be here to assist you at any time. Your success is my priority.
Key Skills:
- Digital IC design
- RTL Coding using Verilog/SystemVerilog and VHDL
- Simulation and debugging using QuestaSim/ModelSim
- STA and CDC
- FPGA/ASIC flow
- Communication protocols such as: UART - SPI - I2C - AXI
- Programming languages such as: Python • C/C++.
- Knowledge in scripting Language : TCL.
- Documentation languages such as: Markdown • Latex.
Tools:
Vivado IDE • Quartus prime • Efinity IDE • VS Code • Xilinx ISE • ModelSim/QuestaSim • Synopsys Deesign Compiler •MATLAB • Git/GitHub • Notepad++.