Digital Verilog Time sensitive
Presupuesto $10-50 USD
Job Description:
1) Frequency divider by - / 2n - / by any integer 2) Serial Peripheral Interface (SPI) - Both master and slave 3) UART TX/RX - Asynchronous serial communication - Start bit, Stop bit, over sampling etc. - Exercise on cross-clock domain synchronizer What to submit - RTL code (.v) with inline comment - Test bench (.v) with inline comment - Timing diagram (gtkwave) with annotation - Rough description of the corresponding circuit
Quick turnaround needed
6 freelancers están ofertando un promedio de $34 por este trabajo
Hey there! I'm a professional electrical engineer having more than 4 years of experience in verilog. Share more details about the task over chat.
Hi There, I am a senior PhD Level Expert and Have more than 5 years of experience in verilog and VHDL coding. Just check my profile and share your details. Time and Budget will be discussed. Thanks
I am a final year student from the Department of Electronics and Electrical Communication Engineering. This is the domain of my interest. I shall be able to do this in a few hours. I have more than 2 years of continuou Más
Valuable client I'm expert electrical engineer with more than 4 years of experience in Verilog coding. I have go through requirements. But, i have few questions in my mind. The turn around will be according to your dea Más
