ASIC IP RTL/TB Development - Automation from Perl to SV files

Job Description :- Automate some Perl to System Verilog Files of a switch testbench. Automate for multiple configurations provided in Perl file. For one of the configurations, a reference testbench is provided. Write scripts to automate TB files such that it matches refernce config and generate for all other config. Make sure simvs are getting built and tests are run. Detailed Requirement :- 1) Preference - Junior 0-4 years of experience engineer or senior around 10 plus years of experience. Experience either in RTL Design or TB/Verification. 2) Experience in VLSI - ASIC/FPGA design with following skillset - a) Verilog, System Verilog, b) Perl, Bash, Make c) working in Unix/Linux Environment and Vim/gvim 3) Following are domain expertise - a) For junor engineers - Intermediate to efficient capability in skillset above. Added advantage is experience in RTL-design and/or verification experience of small to medium sized blocks. b) For senior engineers that have design exposure - experience in building microarchitecture, developing RTL code/bug fixes for decent size of module. c) For senior engineers that have verification exposure - experience in building System Verilog based Testbench development experience, building a testplan. d) Overall exposure to switch, arbitration, ordering, coherency, PCIe etc is added advantage. 4) Soft skills - a) For junior engineers - interest in learning the design/verification as one of primary interest of freelancing alonside earning money b) For junior/senior engineers - passion to explore new domains and happy to solve tough problems. c) For junior/senior engineers - have good energy to finish work in a timely manner, attention to details and humility to learn from right feedback. 5) Time Availability - a) Desirable to have at least 10-15+ hours per week for the work. b) Able to support next 1-2 months minimum.