Course: Computer Organization and Architecture
Project: Design of MIPS Datapath components Using Logisim
Objectives
After completing this project you will:
· Design a 32x 32 bit register file
· Design a 32 bit arithmetic and logic unit (ALU)
Register File
The register file consists of 32 x 32-bit registers and has the following interface as shown
in Figure 1:
_ BusA and BusB: 32-bit output busses for reading 2 registers
_ BusW: 32-bit input bus for writing a register when RegWrite is 1
_ RA selects register to be read on BusA
_ RB selects register to be read on BusB
_ RW selects the register to be written
Hello! Please check my reviews and profile to know more about me and my work.
I’ve implemented such Simulators in the past and Hence I should be able to help you out.
Thank you!
It's an easy project for me. I will complete it with the highest quality for you.
Relevant Skills and Experience
Have 10 years of experience in Asic design and verification. Worked on MIPS mcu design and verification. Master of verilog/systemverilog language
Proposed Milestones
$10 USD - part1
$10 USD - part2
I have well experienced in doing such kind of jobs....................................
Relevant Skills and Experience
verilog/vhdl
Proposed Milestones
$30 USD - i will do my level best
I have worked on 32-bit pipeline processor. so this task will be easy for me
Relevant Skills and Experience
logisim is easy to use for desinging your task
Proposed Milestones
$35 USD - 32-bit pipeline processor
Stay tuned, I'm still working on this proposal.