Standard cells and 16 bit carry look a head adder Using X2GO

Hi, as per discussed in chat. Will complete the work mentioned by Sunday midnight PST. Will deliver a clean work on time.

Dear sir I have more than 10 years experience in digital design using verilog and vhdl please check my profile page also please message me so that we can discuss Best regards

I have long experience with FPGA and VHDL . I work with both intel and Xilinx FPGAs , SoC and SOPC. I use Quartus II and Vivado IDEs accordingly. I test timing compliance through timing analysis . I deliver tested , neat and well-commented code that can be reused or modified for future development. More to be discussed once you contact me . BR, M.T.