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Digital Design Problem, VHDL

$10-30 USD

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Publicado hace casi 8 años

$10-30 USD

Pagado a la entrega
Digital Design problem to solve using VHDL code.
ID del proyecto: 10453896

Información sobre el proyecto

14 propuestas
Proyecto remoto
Activo hace 8 años

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14 freelancers están ofertando un promedio de $23 USD por este trabajo
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Dear sir I have more than 9 years experience in digital design using VHDL please check my profile also please message me so that we can discuss
$25 USD en 1 día
5,0 (234 comentarios)
7,4
7,4
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I can do this task for you.I can do this task for you.I can do this task for you.I can do this task for you.I can do this task for you.
$35 USD en 1 día
4,8 (91 comentarios)
6,1
6,1
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Hello, My name is Mohamed. I have 7 years experience in digital design and HDL. I checked your project about implementing 4 bit parallel adder. I can handle it and deliver it with high accuracy. Contact me for more details. Regards
$25 USD en 0 día
5,0 (20 comentarios)
4,2
4,2
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Hi , I am working as FPGA design engineer since last 6 years and I have expertise in both verilog and VHDL. I can help you in thsi project
$25 USD en 1 día
4,9 (3 comentarios)
3,5
3,5
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Having had four years of experience with a variety of projects I have been exposed to, and absorbed, a great deal of knowledge around system and design engineering. This includes having excellent knowledge of C++, C, Verilog and VHDL languages; experience of using tools such as ASIC, Code Compose Studio, Modelsim and Xilinx Advance Design System; and understanding of System Verilog and UVM methodology. My work experience has seen me carry out a variety of projects from VGA interface, video compression to RF Module Interfacing and RAM / Flash Interfacing.
$10 USD en 1 día
4,2 (1 comentario)
2,1
2,1
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The price and time are negotiable depending on your requirement
$25 USD en 1 día
5,0 (2 comentarios)
1,3
1,3
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A proposal has not yet been provided
$15 USD en 1 día
4,7 (3 comentarios)
1,0
1,0
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Hello, I am an electronics engineer having experience in FPGA based digital system design for more than 3 years. I have designed and delivered many FPGA based digital systems.
$25 USD en 1 día
5,0 (1 comentario)
0,7
0,7
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I have been teaching on VHDL,I have a good basis for digital logic and digital circuits using VHDL been designed using the software for the quarter II 9.0 or later, and is very suitable for your requirements
$25 USD en 10 días
0,0 (0 comentarios)
0,0
0,0
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A proposal has not yet been provided
$25 USD en 2 días
0,0 (0 comentarios)
0,0
0,0
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i can do it in 30mins, guarantee. I tOok this class before and have no trouble doing it. and it is purely logic design, no need for vhdl coding, in my opinion. let me know. thanks
$20 USD en 1 día
0,0 (0 comentarios)
0,0
0,0
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# Currently Working @NXP Semiconductors in VLSI domain # Excelled in FPGA based system designs and ASIC designs # Experience in Verilog HDL for more than 2 years # Designed various Digital designs using Verilog HDL as my research learning @VIT, Vellore
$15 USD en 1 día
0,0 (0 comentarios)
1,7
1,7
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I am Electronic Engineering student . Since your Question corresponds to adder which comes under digital domain . I am the appropriate choice
$20 USD en 2 días
0,0 (0 comentarios)
0,0
0,0
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Hi, This's a relative easy problem. I can give a quick derivation: As you may know, in FULL ADDER LOGIC, Ci+1 = AiBi+AiCi+BiCi, and Si=Ai XOR Bi XOR Ci. In this problem, if you substitute Pi=Ai+Bi, Gi=AiBi for Ci+1 and simplify it, you will get: Ci+1 = (C'iG'i+P'i)' = (C'iG'i)' Pi = (Ci+Gi) Pi = (Ci+AiBi) (Ai+Bi) = AiCi + AiAiBi + BiCi + AiBiBi = AiCi + AiBi + BiCi, which is actually the logic of Ci+1. Similarly, for Si: Si = (PiG'i) XOR Ci = ((Ai+Bi)(AiBi)') XOR Ci = ((Ai + Bi)(A'i + B'i)) XOR Ci = (AiA'i + AiB'i + BiA'i + BiB'i) XOR Ci = (AiB'i + A'iBi) XOR Ci = Ai XOR Bi XOR Ci, which is the logic of Si. In the figure, the NAND gate with inputs A0 and B0 generates G'i, and the NOR gate with inputs A0 and B0 generates P'i. As you require, I am happy to continue the work by providing a VHDL code to simulate this adder logic. I would like to talk with you about more details, and I am looking to hearing from you. Thank you!
$20 USD en 0 día
0,0 (0 comentarios)
0,0
0,0
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8+ Years industry experience with High Speed FPGA Designs in Wireless (CDMA, LTE), Cryptography, DSP(Image Compression, Digital Filters) domains Experienced in all phases of a design; from concept to production, including design definition, simulation, writing testbenches, place & route, fixes, board designing constraints, defining specs, manuals and customer applications support Experienced in using the following design tools: Xilinx Tools (ISE, EDK, SDK, Power Analyzer, ChipScope Soft Logic Analyzer) , Altera Tools (Quartus, SignalTap), Mentor Graphics (ModelSim, HDL Author), TI Code Composer Studio, KEIL MDK Experienced in, C/C++, VHDL, Embedded Application Development, Assembly Language. Experienced in Microsoft Visio for creating flowcharts, design methodologies
$25 USD en 1 día
0,0 (0 comentarios)
0,0
0,0

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Bandera de BOSNIA AND HERZEGOVINA
Sarajevo, Bosnia and Herzegovina
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Miembro desde abr 10, 2015

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