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Project for rohi1710rohi1710

4 freelancers are bidding on average $14 for this job

rohi1710rohi1710

Hired by the Employer

$10 USD en 3 días
(4 comentarios)
4.5
ssi57e814d4beaeb

Writing Verilog HDL codes which can be synthesised is what I do everyday, so give me the opportunity to write verilog codes for complex functions which can be easily synthesised on an FPGA board.

$15 USD en 1 día
(0 comentarios)
0.0
$15 USD en 1 día
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0.0
tulikaranjansmit

I am Tulika Ranjan [url removed, login to view] in VLSI Design from NIT-Surathkal. I have been involved in an internship at NAL and LRDE (DRDO). Presently working with HCL Technologies Ltd. having 2+ years of experience. I am very profess Más

$15 USD en 5 días
(0 comentarios)
0.0