Asic design - Verilog/HDL code -Design -- 2

Cancelado Publicado hace 6 años Pagado a la entrega
Cancelado Pagado a la entrega

Analyze, design, synthesize, and simulate logic circuits using Verilog-HDL and different

widely-used tools such as ModelSim

Verilog / VHDL

Nº del proyecto: #14010647

Sobre el proyecto

9 propuestas Proyecto remoto Activo hace 6 años

9 freelancers están ofertando un promedio de $159 por este trabajo

raulbehl

Hello! I am an experienced Engineer and have been helping out many on this platform. It would be great if I could help you out. Thank you!

$155 USD en 3 días
(63 comentarios)
5.9
jambakhtiar

Hi, How are you. I saw you job. And I'm interested to do it. Let me know if you are willing to work with me.

$200 USD en 6 días
(4 comentarios)
1.5
elamirin

Hi, I am working as an IC Digital Designer consultant since about 10 years now. So I have a strong background in ASIC and FPGA design flow from RTL to GDSII. We can have a first contact to discuss about your needs and Más

$222 USD en 5 días
(0 comentarios)
0.0
weld3li

Hello, I can do this job for free :) Please give me more informations to start about the system you want to implement and i will send you my reply asap, Thank you kind regards

$30 USD en 10 días
(0 comentarios)
0.0