Design and simulate a 4-bit Synchronous Up-Down Counter in Altera Max Plus II.

Please help with this Project; The design that is being asked to simulate is uploaded with the file as a jpg; called Design_1.jpg. The question is asked: Proceed with the design and simulation of a four-bit Up-Down counter; you will need to use Flip-Flops JK negative edge triggered 74112. Implementation with other class of devices, like 71LS161/163 will not be considered. The simulations should use a clock of 25 MHz . You can sketch it or design it on paper. That is fine.