DC/DC Boost Converter Topologies Design Project

Design boost converters with high boost ratios and efficiencies and reasonably low costs of components for specification given. Calculations of component parameters and reasons why the size of components were chosen? Closed loop current and voltage control design (where necessary, with PI blocks, limiters, filters, comparators, voltage sensors, voltmeters, ammeters etc.) with reasons for block use and notes on design. Examples of the style of control needed or attempted is given in the semi-complete schematics. Topologies provided as attachments. Use this specification, Specification 1: P=1MW; Vin = 20kV; Vout=50kV for the 6 schematics design of each topology. I would need an experimental validation circuit for designing a breadboard/ circuit board for a second specification 2: of P=60-100W; Vout = 100Vout_max. (I would like the circuit current and voltage ripples to be limited as much as possible especially for the experimental circuit.) Design the converters for optimum efficiency and show calculation overall efficiency; also design for lowest losses with reason for use of components and how they increase efficiency of reduce losses. There are 6 topologies/ circuits. I'm trying to do an investigation looking at installed power in the semiconductors, size of passive components, evaluation of losses in semiconductors, losses in magnetic components and overall efficiency (so i need all these results with calculations, equations and reasons for use). Save SimView figures of Gate Signals, Voltages signals, Current signals, Voltage ripples, Current ripples, inductor currents, capacitors figures, Processed power against Installed Power and evaluation of losses (including magnetic losses) [login to view URL] provide notes and calculations of losses. Report via notes or sentences on describing the figures. Require files to be saved in PSIM 9.0. If you require reference papers for assistance, I can attach them as well. Need completion in 3-4 days and a start as soon as possible.