necesito realizar proyectos en la tarjeta Nexys 2 vhdl del fabricante que tiene el procesador spartan 3E de xilinx practicamente lo que busco es un manual tecnico de como descargar los softwares necesarios para el trabajo, describir paso a paso de como realizar un programa utilizando el puerto vga de la tarjeta , en concreto un programa completo basado
Soy de colombia Programar un juego llamado simon dice En VHDL y en el programa llamado Xilinx Simón dice Colores El juego Simón dice colores es un juego de memoria donde el jugador deberá seguir la secuencia de colores que “Simón” aleatoriamente va generando. cada uno asociado con un color (verde, amarillo, azul y rojo). Cada
1. Configure 4 UARTs (Rx Only). 2. Configure 2 SPI Slaves. 3. Data coming on UARTs are split into two groups. a. 2 UARTs first SPI slave and another 2 UART data Second SPI slave. 4. Data pattern on UART will be "Magicnumber(4 bytes), Length (4 bytes), Payload".
...Proficient in Verilog/VDHL and C/C++ - Experienced with Xilinx Vivado - Experienced in debugging on ILA/JTAG Preferred Qualifications: - Familiar with AXI interface - Familiar with wireless communication system VLNComm has several current working FPGA projects and one incomplete FPGA project in development on the topic of visible light communication
Setting up Xilinx ZCU102 board for Petalinux flow, using on-board DDR, functions include HDMI input, HDMI output, and customer provided IP interface. Also looking for firmware development tool chain setup.
...The system includes an FPGA part. We use Xilinx Vivado as our development platform and Xilinx all programmable SoC as our hardware platform. The project involves transmitter and receiver design. We have implemented 4-PAM (pulse amplitude modulation) and one feature to remove the unwanted interference. The project is not complete and requires troubleshooting
I have a code in Matlab, need to be converted to c to be able to run it on Vivado HLS tool. however, this too doesn't synthesize dynamic memory or pointers or C random functions. The memory has to be static and no pointers.
The firmware will need to have base functions for interfacing the Bluetooth...firmware will need to have base functions for interfacing the Bluetooth radio and other communication (i.e. UART, SD Card, Ethernet, etc. ) and loading the memory. Using Xilinx, VIVADO software. and also PicoZed 7010 SOM + FMC Carrier V2 (xc7z010clg400-1) processing system
I am a cryptocurrency miner, and I would like to buy a larger number of FPGA cards to mine with, specifically the Xilinx VCU1525 FPGA Card. I need someone to Program the card to mine a number of specific algorithms. Preferably the dagger hashimoto, Neoscrypt, Equihash algorithms, I need a quote on how much this will cost.
We are seeking a consultant to migrate several Xilinx K7, K7 Ultra and/or V7 FPGA-based DSP Apps (developed using Vivado) to OpenCL so they can run on Intel, AMD/ATI, NVIDIA and mobile GPUs. Ideally, the OpenCL acceleration would fit into our existing Windows / LabVIEW framework so we could have compatibility with our current set of apps.
Design Pipeline processor for RISC based instruction set on Xilinx ISE verilog for Spartan 3E board. Instruction set is given and we need certain kind of output based on designed assembly code. Code should be loaded on Instruction memory and it's already done. we have only 2 days for that but processor is 8bit and instruction is 16bit
I am looking at an FPGA project using xilinx the project has very specific functions that i do not have the skills required to implement it myself sadly so i hope you can help with that. The project is for a crypto miner that can mine using the cryptonote algorithm Variant 1 i have chosen a model of FPGA as it has 100k logic gates and good memory